Improving DTSVLIW Performance via Block Compaction

 Dynamically Trace Scheduled VLIW (DTSVLIW) machines have two execution engines and two instruction caches: a Scheduler Engine and a VLIW Engine, and an Instruction Cache and a VLIW Cache. The Scheduler Engine fetches instructions from the Instruction Cache and executes them singly, the first time, using a simple pipelined processor. In addition, it dynamically schedules the instruction trace produced during this execution into VLIW instructions, groups them as blocks of VLIW instructions, and saves these blocks into the VLIW Cache. If the same instruction trace must be executed again, it is fetched by the VLIW Engine from this cache and executed in VLIW fashion. Due to code temporal execution locality, machines that follow the DTSVLIW architecture spend most of the time operating in VLIW mode, which results in instruction-level parallelism (ILP) comparable or better than other current approaches for exploiting ILP, such as superscalar or pure VLIW. However, the scheduled blocks may contain a large number of nop instructions in VLIW instructions’ slots that the Scheduler Engine has been unable to fill with useful instructions. In this paper we present two techniques for compacting blocks that allow removing part of these nop instructions dynamically. Our experiments show that DTSVLIW machines that employ these techniques can perform 13.2% better than DTSVLIW machines that do not. Keywords DTSVLIW, VLIW, instruction compaction